1. Field of the Invention
The present invention relates to a semiconductor device, particularly to a semiconductor device of a surface package type including a redistribution wiring and conductive post, and to a method of manufacturing the same.
This application is a counterpart of Japanese patent application, Serial Number 327662/2002, filed Nov. 12, 2002, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
With miniaturization of a portable apparatus, there has been a demand for miniaturization of a semiconductor device mounted on the apparatus. To meet this demand, the semiconductor device referred to as a chip size package (CSP) which has substantially the same size as an outer dimension of a semiconductor chip has appeared. Examples of a mode of CSP include a wafer-level chip size/scale package (WCSP), and a multi chip package (MCP) in which a plurality of semiconductor chips are embedded in one package.
FIG. 2 is a schematic sectional view showing the semiconductor device having a prior-art MCP structure described in Patent Document 1 (Japanese Patent Application Laid-Open No. 11-219984, FIG. 1). Since FIG. 2 is a schematic sectional view, for the convenience of description, reference numerals in FIG. 2 do not agree with those in Patent Document 1.
This semiconductor device is of an MCP type which includes a first chip 10 and second chip 20 and in which these chips are stacked/mounted on a substrate 30 and whose surface is resin-sealed.
In the first chip 10, gold bumps 13 for connection are formed on a bonding pad 12 disposed in the surface of a semiconductor substrate 11, that is, a circuit forming surface. In the second chip 20, bonding pads 22 are formed in the circuit forming surface of a semiconductor substrate 21.
The first chip 10 and second chip 20 are mounted on the substrate 30, and electrically/mechanically connected to a printed wiring board via the substrate. Bonding pads 32 are formed on the chip mounting surface of an insulating base material 31, and ball pads 33 are formed in an external connection surface. The bonding pads 32 are disposed opposite to the ball pads 33 via the base material 31, and the pads are connected to each other via each conductive via posts 34. Moreover, solder bumps 35 to be connected to the printed wiring board are formed on the ball pads 33.
The substrate 30 is flip-chip connected to the first chip 10. That is, the circuit forming surface of the first chip 10 is mounted opposite to the chip mounting surface of the substrate 30. The bonding pads 32 on a substrate 30 side are electrically connected to the bonding pads 12 on a first chip side by the gold bumps 13. Furthermore, the substrate 30 is fixed to the first chip 10 by an anisotropically conductive or non-conductive adhesive 41.
The back surface of the second chip 20 is fixed to that of the first chip 10 by an adhesive 42. The bonding pads 22 of the second chip 20 surface are connected to the bonding pads 32 of the substrate 30 by wires 43 such as gold wires using a wire bonding technique. Gold balls 23 generated at a time of wire bonding are formed on the bonding pads 22. Moreover, the first chip 10, second chip 20, and wires 43 are sealed with a seal resin 44, and protected from an external environment.
However, the prior-art semiconductor device has the following two problems.
A first problem is that an adhesive 41 is used to fix the first chip 10 to the substrate 30. Since the adhesive 41 generally has hygroscopicity, the adhesive absorbs moisture in a manufacturing process of a package or under use environment of the completed package, and easily peels. Furthermore, when this semiconductor device is mounted on a printed wiring board and connected to the board by reflow, the moisture absorbed in the adhesive 41 forms water vapor and explodes by the heat of reflow. This causes a problem that the semiconductor device breaks and the substrate 30 is disconnected from the first chip 10. Another problem is that a long processing time for adding pressure and temperature to harden the adhesive 41 is required, and mass productivity is inferior.
A second problem is that the first chip 10 is flip-chip connected to the substrate 30. Therefore, the positions of the bonding pads 12 of the first chip 10 need to have a one-to-one correspondence with those of the bonding pads 32 of the substrate 30. An interval between the bonding pads 12 of the first chip 10 tends to be narrowed by an increase of integration or the number of signal lines for external connection, but there is a limitation in narrowing the interval between the bonding pads 32 of the substrate 30 (the interval is about 100 μm in a general substrate, and about 70 μm in a built-up substrate). Therefore, the number of bonding pads 12 of the first chip 10 is large. When a pitch is narrow, there is a problem that a flip-chip structure shown in FIG. 2 cannot be employed.